1. Field of the Invention
The present invention relates to a nonvolatile memory device which can write, read, and erase data electrically.
2. Description of the Related Art
As a memory device, a dynamic random access memory (DRAM) and a static random access memory (SRAM) which are categorized as a volatile memory; a mask read only memory (ROM), an electrically programmable read only memory (EPROM), an electrically erasable and programmable read only memory (EEPROM), a flash memory, and a ferroelectric random access memory which are categorized as a nonvolatile memory; and the like are given. Among the above memory devices, flash memories are widely marketed, which are mainly used for mobile storage media such as USB memories and memory cards. The reason of this is that flash memories are resistant to physical impact and can be conveniently used because they are non-volatile memories which can repeatedly write and delete data and can store data without being supplied with power.
The types of flash memory include NAND flash memories in which a plurality of memory cells is connected in series and NOR flash memories in which a plurality of memory cells is arranged in a matrix. Both of these flash memories have a transistor which functions as a memory element in each memory cell. Further, the transistor which functions as a memory element has a layer for accumulating electric charge, which is called floating gate, between a control gate and a channel region formed in a semiconductor substrate. The accumulation of electric charge in the floating gate enables storage of data (see Patent Document 1).
A NAND memory device includes a plurality of NAND cell units each including a plurality of adjacent memory cells. In each NAND cell unit, memory cells are connected in series and each memory cell has a common source or drain (an impurity region) with an adjacent memory cell. One of terminals of each NAND cell unit is connected to a common source line via a first selection transistor. The other of the terminals of each NAND cell unit is connected to a bit line via a second selection transistor. In the memory device, the selection gates of the first selection transistors connected to the respective NAND cell units are connected to one another; the selection gates of the second selection transistors connected to the respective NAND cell units are also connected to one another; the control gates of the memory cells in the same row are connected to one another.
In the NAND memory device, after a memory cell is put in an erased state, i.e., the memory cell is set to “1”, “0” is written into the memory cell. In order to write “0” into the memory cell, one of the first selection transistor and the second selection transistor is turned off and the other is turned on. On the other hand, in order to hold “1” in the memory cell, the first selection transistor and the second selection transistor are both turned off.